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| NTE7049 Integrated Circuit CMOS-Sync Generator for TV & Video Processing Systems Description: The NTE7049 is a CMOS LSI sync generator in a 24-Lead DIP type package that produces all the timing signals required to drive a fully 2-to-1 interlaced 525-line 30-frame/second, or 625-line 25-frame/second TV camera or video processing system. A complete sync waveform is produced which begins each field with six serrated vertical sync pulses, preceded and followed by six half-width double frequency equalizing pulses. The sync output is gated by the master clock to preserve horizontal phase continuity during the vertical interval. The NTE7049 can be operated either in "genlock" mode, in which it is synchronized with a reference sync pulse train from another TV camera, or in "stand-alone" mode, in which it is synchronized with a local on-chip crystal oscillator (the crystal and two passive components are off chip). Also, the circuit can sense the presence or absence of a reference sync pulse train and automatically select the "genlock" or "stand-alone" mode. A frame sync pulse is produced at the beginning of every odd field. The vertical counter can be reset to either the first equalizing pulse or the first vertical sync pulse of the vertical interval. Features: D Interlaced Composite Sync Output D Automatic Genlock Capability D Crystal Oscillator Operation D 525 or 625 Line Operation D Vertical Reset Option D Wide Power Supply Operating Voltage: 4V to 15V Applications: D Cameras D Monitors and Displays D CATV D Teletext D Video Games D Sync Restorer D Video Service Instruments Absolute Maximum Ratings: DC Supply Voltage (Voltage referenced to VSS terminal), VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V Input Voltage Range (All Inputs), VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS VI VDD DC Input Current (Any One Input), II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA Power Dissipation (TA = -40 to +60C), PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW Derate Linearly Above +60C to 200mW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12mW/C Device Dissipation Per Output Transistor (TA = -40 to +85C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +85C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to +150C Lead Temperature (During Soldering, 1/16 1/32 from case for 10sec), TL . . . . . . . . . . . . . . . . . . . . . . +265C Static Electrical Characteristics: (TA = +25C unless otherwise specified) Parameter Quiescent Device Current Symbol IDD Test Conditions VDD = 5V VDD = 10V VDD = 15V Output Voltage, Low Level Output Voltage, High Level Threshold Voltage, N-Channel Threshold Voltage, P-Channel Noise Immunity (Any Input) Low Level High Level Output SINK Current, N-Channel VOL VOH VTHN VTHP VNL VNH IDN VDD = 5V VDD = 10V VDD = 5V VDD = 10V ID = 10A ID = 10A VDD = 5V VDD = 10V VDD = 5V VDD = 10V VDD = 5V VDD = 10V Output SOURCE Current, P-Channel IDP VDD = 5V VDD = 10V Input Current (Each Input) II VO = 0.5V VO = 5V VO = 0.5V VO = 10V VO = 4.5V VO = 0V VO = 9.5V VO = 0V Min 0.5 1.5 3.0 - - 4.99 9.99 1.0 -1.0 1.5 3.0 1.5 3.0 80 960 200 2400 80 960 200 2400 - Typ 0.75 2.0 4.0 - - - - 1.5 -1.5 2.25 4.5 2.25 4.5 160 1920 400 4800 160 1920 400 4800 10 Max 1.0 2.5 5.0 0.01 0.01 - - 2.6 -2.6 - - - - - - - - - - - - - Unit mA mA mA V V V V V V V V V V A A A A A A A A pA Dynamic Electrical Characteristics: (TA = +25C, CL = 15pF, Note 1 unless otherwise specified) Parameter Output State Propagation Delay Time (50% to 50%) Low-to-High Level High-to-Low Level Transition Time (10% to 90%) Low-to-High High-to-Low Input Capacity (Per Input) Symbol Test Conditions Min Typ Max Unit tPLH tPHL VDD = 5V VDD = 10V - - 40 20 80 40 ns ns tTLH tTHL CI VDD = 5V VDD = 10V - - - 45 30 5 90 60 - ns ns pF Note 1. Typical temperature coefficient for all values of VDD = 0.3%/C. Pin Connection Diagram Delay, Genlock to Crystal OSC Crystal OSC Feedback Tap 1 2 24 Resistor Connection for Genlock OSC 23 Master Frequency Input 22 R/C Connection for Genlock OSC 21 Delay, Genlock to Crystal OSC 20 Genlock Input (Composite Sync) 19 VDD 18 525 Line to 625 Line Operation Switch 17 Vertical Processing Blanking Output 16 Short Vertical Drive Output 15 Frame Sync Output (Odd Field) 14 Horizontal Processing Blanking Output 13 Mixed Processing Blanking Output VSS 3 Horizontal Drive Output Mixed Sync Output Genlock OSC Capacitor Connection Mixed Beam Blanking Output 4 5 6 7 Vertical Counter Reset 8 to First Equalizing Pulse Vertical Drive Output 9 Vertical Reset to 10 First Vertical Sync Pulse Horizontal Clamp Output 11 VSS 12 24 13 1 12 1.300 (33.02) Max .520 (13.2) .225 (5.73) Max .100 (2.54) 1.100 (27.94) .126 (3.22) Min .600 (15.24) |
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